Janez Bitenc was born in Kranj, Slovenia in 1978. He received the B.S. degree in electro technical engineer from University of Ljubljana FE in 2001. Since 2001 he has been employed in Iskraemeco where he performed first as a hardware design engineer, project manager, team leader. His current research interests include component management, material science, novel approach of design for reliability, PLM approach that enable management of component data and also quality management specifically root cause analysis and process optimization.